CRG Requirement to Design
SkillFiles & storageConvert a CRG requirement table into clock/reset design tables, PLL recommendations, and an architecture report. Use before clock/reset diagram generation when requirements are supplied as Excel or CSV.
Available today. Use it from your connected AI after setup.
No other account needed.
Connect ahel once, and every AI you use reads what you have installed.
Then ask your AI: use the CRG Requirement to Design skill
What this skill tells your AI
The instructions your AI receives, as published by siliconpeasant/vibe_soc in .agents/skills/crg-req-to-design/SKILL.md and read by ahel’s review.
Call crg_req_to_design with an existing .xlsx, .xls, or .csv requirement table and optional output directory. The default is <input-stem>_design/ beside the input.
Recognized concepts include subsystem/IP, clock/reset signal name, frequency/note, pad sources, integer dividers, and reset roots. Outputs are:
clock_design.xlsxreset_design.xlsxcrg_report.txt
Review PLL/divider recommendations and missing-frequency signals before treating the design table as approved. Feed reviewed tables to cr-tree-diag-gen for visualization.
This Skill creates design tables only. It does not generate CRG RTL; after design tables are reviewed, use the registered crg-gen.crg_gen tool for RTL/SDC generation.
Signals
- GitHub stars
- 38
- Forks
- 18
- Last commit
- Aug 2026
Advanced
- Catalog kind
- skill
- Gateway key
crg-req-to-design- Source
- github.com/siliconpeasant/vibe_soc