Domain Layer Module
SkillDev toolsGives your agent guidance for working on electronics build code like netlists, PCB generation, and BOM exporters.
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About this capability
Instructions for electronics-specific logic and build processes: netlists, PCBs, build steps, and exporters. Use when implementing or modifying build steps, exporters, PCB generation, or BOM/netlist output.
What this skill tells your AI
The instructions your AI receives, as published by atopile/atopile in .claude/skills/domain-layer/SKILL.md and read by ahel’s review.
The domain layer (primarily src/atopile/build_steps.py and src/faebryk/exporters/) encompasses the logic and processes specific to electronic hardware engineering. This includes the build pipeline that transforms a compiled graph into manufacturing artifacts (Gerbers, BOMs, Pick & Place).
Quick Start
Run the standard build pipeline from a project directory (where ato.yaml lives):
ato build
Relevant Files
- Build Orchestration:
src/atopile/build_steps.py- Defines the
Musterclass (a DAG-based task runner). - Registers standard build targets:
generate_bom,generate_manufacturing_data,update_pcb, etc.
- Defines the
- Build entry / app init:
src/atopile/build.py(constructs app graph from.atoor.py, runs unit inference) - Exporters:
src/faebryk/exporters/- pcb/: KiCad PCB generation and layout sync (
layout_sync.py). - bom/: Bill of Materials generation (
jlcpcb.py, etc.). - netlist/: Netlist formatting.
- documentation/: Datasheets, diagrams.
- pcb/: KiCad PCB generation and layout sync (
- Layout sync inputs:
src/atopile/layout.py(generates.layouts.jsonmodule→layout mapping)src/atopile/kicad_plugin/README.md(plugin workflow overview)
Dependants (Call Sites)
- CLI (
src/atopile/cli/build.py): Theato buildcommand directly invokesbuild_steps.musterto execute the pipeline. - IDE/Extension: May invoke specific build steps for previews (e.g.,
generate_3d_render).
How to Work With / Develop / Test
Core Concepts
- Muster: The task runner. Targets declare dependencies (e.g.
generate_bomdepends onbuild_design). - Layout Sync: The process of preserving manual PCB layout changes while updating the netlist/components from the code (
update_pcb). - Artifacts: Files produced by the build process, stored in the build directory.
Development Workflow
- Adding a Config Option: If a new build step needs configuration, add it to
atopile.config(not covered here, but relevant). - New Exporters: Create a new module in
src/faebryk/exporters/and register a wrapper function inbuild_steps.pyusing@muster.register.
Testing
- Integration Tests: Since this layer orchestrates the whole flow, it is best tested via end-to-end tests or integration tests in
test/end_to_end/ortest/integration/. - Manual Verification: Run
ato buildon a sample project and inspect the generated artifacts (Gerbers, BOM csv). - Muster unit tests:
ato dev test --llm test/test_muster.py -q
Best Practices
- Idempotency: Build steps should generally be idempotent.
- Virtual Targets: Use
virtual=Truefor targets that just group other targets (e.g.allordefault). - Layout Preservation: Be extremely careful when modifying
update_pcborlayout_synclogic to avoid dataloss of user's manual PCB routing.
Signals
- GitHub stars
- 4k
- Forks
- 234
- Last commit
- Jun 2026
Advanced
- Catalog kind
- skill
- Gateway key
domain-layer- Source
- github.com/atopile/atopile