SoC Integrate
SkillDev toolsExtract RTL ports, generate instances/wrappers/top modules, and track interface changes through snapshots and integration configs. Use for generated SoC top-level integration and port-change maintenance.
Available today. Use it from your connected AI after setup.
No other account needed.
Connect ahel once, and every AI you use reads what you have installed.
Then ask your AI: use the SoC Integrate skill
What this skill tells your AI
The instructions your AI receives, as published by siliconpeasant/vibe_soc in .agents/skills/soc-integrate/SKILL.md and read by ahel’s review.
Use the registered soc-integrate MCP server; do not invoke the Python CLI as a fallback.
Tools:
soc_extract,soc_instantiate,soc_wrap,soc_csvsoc_integrate,soc_extract_map,soc_update,soc_removesoc_snapshot,soc_diff
soc_integrate emits the generated top, .integrate.json, and review CSV. Preserve manual connection intent through a port-map JSON and refresh with soc_update; do not hand-edit generated instances.
Automatic shared-signal rules are suitable only for simple direction/width-compatible ports. Review multiple-driver, width, reset-domain, clock-domain, and protocol connections explicitly.
The built-in parser supports ANSI-style Verilog/SystemVerilog module ports. Unsupported syntax must fail explicitly rather than silently dropping ports. For interfaces, modports, complex package types, or non-ANSI declarations, provide a normalized wrapper before integration.
Signals
- GitHub stars
- 38
- Forks
- 18
- Last commit
- Aug 2026
Advanced
- Catalog kind
- skill
- Gateway key
soc-integrate- Source
- github.com/siliconpeasant/vibe_soc